Timing-related defects in Very Large Scale Integrated (“VLSI”) circuits have been a reliability concern with smaller feature sizes and the resulting deep sub-micron effects. Consequently, at-speed testing approaches have been employed, with the test designed to screen out performance-related failures. The manual generation of functional patterns, however, can generally be hampered by the design complexity, which can mandate automatic test pattern generation enabled by structural scan-based testing methods.
Scan-based at-speed testing can utilize load, launch and capture operations for every test pattern. Load operations can be performed via scan/shift operations, filling up all the scan chains with the pattern. As the targeted defects can be timing related, these patterns can check whether transitions launched from scan cells can arrive at their destinations (e.g., scan cells) within a functional clock period.
Currently, there are two different procedures for launching transitions off the serially loaded pattern. As shown in FIG. 1, in LOC, or broadside test 105 (see, e.g., Reference 1), a functional capture operation can launch transitions from the locations where the serially loaded pattern (V1) can differ from the response of the combinational logic to (V1), for example, the launch pattern (V2). In launch-off-shift (“LOS” or skewed-load) test 110 (see, e.g., Reference 2), a single-cycle shift operation can launch transitions from the locations where the serially loaded pattern (V1) can differ from its one-bit shifted version, for example, the launch pattern (V2). In both procedures, a subsequent fast functional capture operation, which can be of a functional clock period apart from the launch event, can set a deadline for the transitions to arrive at their destinations; a timing related defect that slows down the chip below its rated clock speed can thus be exposed.).
Serial shift operations during scan can result in excessive switching activity in the scan chains, which can propagate into the combinational logic, dissipating further dynamic power unnecessarily in both static and at-speed testing procedures. This can result in an unexpected behavior of the design, which can result in a yield loss, or reliability problems. Elevated levels of peak power, which can be the maximum instantaneous power throughout the entire test process, can be the cause of the former problem, while the underlying reason for the latter problem can be the average power that can be the total power dissipation averaged over the duration of the test application process. (See, e.g., References 3 and 4). As the test application process can be dominated by shift operations, average power can mostly depend on shift power, and thus, the impact of launch/capture power on average power can be negligible. Launch/capture power can be more of a concern when peak power can be the targeted issue.
A yield loss problem can be further exacerbated in at-speed testing procedures. (See, e.g., References 5 and 6). Excessive switching activity during the launch cycle can result in elevated peak supply currents, which can lead to an IR drop that can increase the signal propagation delays in the combinational logic. The end-effect cannot be differentiated from that of a timing-related defect, causing a functional chip to fail the at-speed test. A peak power, during the launch cycle of at-speed testing, can therefore be reduced in order to avoid the yield loss induced by IR drop.
A significant amount of research has been done to try to reduce power dissipation during the launch and capture of at-speed testing. Test pattern generation can be done in order to produce patterns that can disable parts of the design during launch and capture (see, e.g., References 7 and 8), and to reduce peak power at the expense of pattern count inflation. Another approach that can elevate pattern count while reducing peak launch power can be in the form of generating patterns under the constraint that only one chain can launch transitions while all chains can capture. (See, e.g., Reference 9). A partitioning approach can be used (see, e.g., Reference 10), whereby power wise costly patterns can be further analyzed via fault simulation to identify the location of the care bits, which can dictate the partitioning of the design during capture. With few problematic patterns, such an approach can deliver power saving albeit at the expense of ancillary defect coverage loss, as the analysis can be fault model dependent.
A judicious x-fill approach driven by an analysis of the responses repetitively produced by the combinational logic can be used. (See, e.g., Reference 11). As with other x-fill approaches, pattern count inflation can be the side effect. Another x-fill approach (see, e.g., Reference 12) can retain pattern count and fault coverage, while it cannot guarantee the same level of defect coverage. Partitioning the design, and testing one partition at a time has been proposed to reduce launch and capture power in a Built-In-Self-Test (“BIST”) (see, e.g., Reference 13), in LOS (see, e.g., Reference 14), and in LOC (see, e.g., Reference 15) testing procedures. In both procedures, newly generated patterns targeting one partition at a time end up loading the interface registers of other partitions as well, incurring a test time and data volume penalty. A similar end-result can be experienced even when the design can be partitioned via Integer Linear Programming (“ILP”), which can minimize capture violations. (See, e.g., Reference 16). For such violations, additional test patterns, such as those having of a high sequential depth, can be generated in order to cover the faults missed due to capture violations, while leaving some of the un-modeled defects uncovered.
Thus, it may be beneficial to provide an exemplary design for testing (“DfT”) solution, which can reduce launch and capture power in LOC, and which can overcome at least some of the deficiencies described herein above.